1. Field of the Invention
The present invention generally relates to a failure testing method for a dynamic random access memory (DRAM), and more particularly, to a leakage testing method for a DRAM having a recess gate.
2. Description of Related Art
Ultra-Large Scale Integration (ULSI) technology is being progressively developed, and correspondingly, very small defects generated during the processing become a critical role determining the occurrence of an ULSI circuit. Recently, a failure test process testing failures occurred during the processing has become a necessary standard procedure of the processing.
Regarding a DRAM, a gross function test is often executed to the memory element, in which a simply reading/writing test for determining whether the product is acceptable or rejected. A failure of a memory element determined during such a gross function test is attributed to a physical failure. Then, those products determined as acceptable during the gross function test will be executed with a leakage test for finding out rejected products for guaranteeing the quality of the products.
However, when the IC circuit processing is progressed further to a sub-micro scale, while the memory element is developed from a 2-dimensional structure to a 3-dimensional structure, the failure mechanism becomes more complicated and more difficult to find out the exact reason of the failures.